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How to check PCB design error

Author : Luwis Date : 2014-5-18 23:50:59
 Whether you are newly printed circuit board design layman , or circuit board design expert , you sometimes circuit board design will always lead to electric shock Naogua Zi like a short circuit , so that some of the usual circuit board design error in the his heart think is a very good board design drawings , this casual board design errors can only put yourself in front of the circuit board design drawings compare our Checklist , found himself the word line drawing board error bars :

A phenomenon : PCB design do not ask this board , with a fine point on the line , it automatically cloth

Comments : automatic routing PCB is bound to occupy a larger area , while producing via multiple times better than manual routing in large quantities of products, PCB factory price factors considered in addition to the business factors that width and over number of holes , which are affecting the quantity consumed PCB yield and drill , saving the cost of the supplier , it found a reason to cut prices .

Phenomenon II : These bus signals are used resistive pull , feeling more at ease .

Comments: The reason for the drop-down signal on the need for many , but not all of them have to pull . A simple pull- down resistor on the input signal, the current also tens of microamperes or less, but a pull- up signal is driven , the current will reach milliamps , the current system is often the address data 32 , there may be 244 /245 bus after isolation and other signals are on the pull , then a few watts power consumption in these resistors on it.

Three phenomena : these unused I CPU and FPGA / O port how to handle it ? Let it empty it, later.

Comments: The unused I / O port if vacant , then a little bit of interference by outsiders may become a repeated oscillation of the input signal , and the power consumption of the basic MOS devices depends on the number of gates flip . If you put it on , then pull each pin will have microampere currents , so the best way is to set the output ( of course, there are other drivers can not pick out a signal )

Phenomenon IV: The FPGA left so many doors used up , you can enjoy playing it

Comments : FGPA power consumption and the number of flip-flops to be used and the number of turns is proportional , so the same type of FPGA 100 times may vary at different times in different circuits of power consumption. Minimize the number of flip-flop flip -speed FPGA power consumption is to reduce the fundamental methods.

Phenomenon V: These small chip's power consumption is very low , do not consider

Comment: For internal power dissipation is less complex chips is difficult to determine , it is mainly determined by the current pin, a ABT16244, no load , then probably less than 1 mA power consumption , but it is an indicator of each foot can drive 60 mA of load ( such as matching tens of ohms ) , the full-load power consumption up to 60 * 16 = 960mA, of course, the supply current is only so big , the heat fell on load bodies.

Phenomenon Six: There are so many memory control signals , I just use this board OE and WE signals can, chip select bar on the ground , so that when the data is read out much faster .

Comments : In most cases the power consumption of the memory chip selected ( regardless of how the OE and WE ) inactive chip select more than 100 times , it should be possible to use the CS control chip , and in a way to meet the other requirements may reduce the chip select pulse width.

Phenomenon Seven: how these signals have had Charge ? As long as the match well, can be eliminated

Comment: Apart from a few specific signal outside ( such as 100BASE-T, CML), are all overshoot , if not great, does not necessarily need to match , even if it is not matched to match best. Like TTL output impedance of less than 50 ohms, 20 ohms or even if it matches with so much resistance , then the current is very large , the power consumption is unacceptable , another signal amplitude will be too small to be used, Besides the general output signal at the output impedance and high output low level is not the same , there is no way to do an exact match. So for TTL, LVDS, and other signals of 422 matches overshoot is acceptable as long as you can .

Phenomenon Eight: lower power consumption are the hardware personnel matter, and the software does not matter.

Review : Hardware just take a stage , singing is the software , visit almost every chip on the bus flipped almost every signal controlled by the software , if the software can reduce the external memory access times ( multi- use register variables , more use of internal CACHE , etc. ) , a timely response to interrupt ( active low and is often a pull-up resistor ) and other specific measures to fight with all the specific board will make a significant contribution to reducing power consumption .

There are 14 recorded originally , and now found only eight , everyone would be on their own circuit board design drawings see if there are more than eight errors committed it !
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